By Ed Sperling
Mentor Graphics added embedded memories to its cell characterization and analysis platform, addressing a growing challenge of excessive runtimes in large circuits. The automated flow runs netlist reduction, all simulations and creates library files.
Cadence rolled out energy-efficient PCI Express 3.0 IP that it claims reduces standby current by 100 times with advanced power and clock management. The IP also includes optimized transition time between active and sleep states.
Synopsys, meanwhile, introduced its M-PCIe, which provides interoperability between the MIPI M-PHY and M-PCIe controller IP for low-power designs. Synopsys also is collaborating with UMC on 14nm finFETs, validating its IP portfolio and parasitic extraction tools. In addition, Synopsys is working with A*STAR IME to optimize through-silicon interposer technology for 2.5D stacked die designs.
Dassault Systemes leveraged its process and product management tools and expertise into an adjacent market—pharmaceuticals and biotech. Process and product lifecycle management are core to the semiconductor market, but they are applicable in other markets, as well.
Semico Research issued a new report that shows total SoC design costs increased 48% from 28nm to 20nm, and will increase another 31% at 14nm and 35% at 10nm. Software design costs increased 102% at 28nm, and are expected to increase at a CAGR of 79% through 10nm. In real terms, that means a 20nm chip with a $20 ASP will break even with 9.238 million units.
The post-PC move to mobile devices will consume more DRAM than PCs by 2015, according to IHS. The firm predicts consumption of DRAM in mobile devices will be $11.6 billion in two years, compared with $9.9 billion for PCs. While that’s about even with PC DRAM consumption this year, the numbers will hit historic highs beginning in 2016.